The present invention relates to a pipeline processor for dividing an instruction into a plurality of stages so as to carry out pipeline processing, and more particularly to a pipeline processor for transferring data obtained by instruction execution to another instruction at a high speed.
In an information processor according to the prior art, an instruction is divided into a plurality of stages, a next instruction stage is executed when the execution of an instruction stage is completed, so that the result of an instruction is obtained every stage execution time to enhance a processing speed. Thus, an information processor for dividing an instruction into a plurality of stages for execution is referred to as a pipeline processor.
Referring to the pipeline processor described above, each instruction is divided into an instruction read-out stage (IF stage), an instruction decode stage (DEC stage), an execution stage (EX stage), a memory stage (MEM stage) and a write stage (WB stage) for execution. In the IF stage, an instruction is read out. In the DEC stage, the instruction is decoded and data is read out from a register file. In the EX stage, an operation specified by the instruction is executed. In the MEM stage, a memory is accessed if the instruction is a load or store instruction. In the WB stage, the data is stored in the register file.
The pipeline processor according to the prior art will be described with reference to the drawings.